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dma_0

altera_avalon_dma v15.1

Parameters allowByteTransactions true allowDoubleWordTransactions true allowHalfWordTransactions true allowQuadWordTransactions true allowWordTransactions true bigEndian false burstEnable true softresetEnable true fifoDepth 32 maxBurstSize 128 minimumDmaTransactionRegisterWidth 13 useRegistersForFIFO false avalonSpec 2.0 readAddressMap <address-map><slave name='pcie_hard_ip_0.txs' start='0x0' end='0x200000' /><slave name='onchip_memory2_0.s1' start='0x200000' end='0x201000' /></address-map> readSlaveAddressWidthMax 22 readSlaveDataWidthMax 64 writeAddressMap <address-map><slave name='pcie_hard_ip_0.txs' start='0x0' end='0x200000' /><slave name='onchip_memory2_0.s1' start='0x200000' end='0x201000' /></address-map> writeSlaveAddressWidthMax 22 writeSlaveDataWidthMax 64 actualDmaTransactionRegisterWidth 22 allowLegacySignals false minimumNumberOfByteTransfers 8191 readMaximumSlaveSpan 2097152 writeMaximumSlaveSpan 2097152 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ALLOW_BYTE_TRANSACTIONS 1 ALLOW_DOUBLEWORD_TRANSACTIONS 1 ALLOW_HW_TRANSACTIONS 1 ALLOW_QUADWORD_TRANSACTIONS 1 ALLOW_WORD_TRANSACTIONS 1 LENGTHWIDTH 13 MAX_BURST_SIZE 128

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onchip_memory2_0

altera_avalon_onchip_memory2 v15.1

Parameters allowInSystemMemoryContentEditor false blockType AUTO dataWidth 32 dualPort false initMemContent true initializationFileName onchip_mem.hex instanceID NONE memorySize 4096 readDuringWriteMode DONT_CARE simAllowMRAMContentsFile false simMemInitOnlyFilename 0 singleClockOperation false slave1Latency 1 slave2Latency 1 useNonDefaultInitFile false copyInitFile false useShallowMemBlocks false writable true ecc_enabled false resetrequest_enabled true autoInitializationFileName pcie_onchip_memory2_0 deviceFamily STINGRAY deviceFeatures ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 1 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 derived_set_addr_width 10 derived_set_data_width 32 derived_gui_ram_block_type Automatic derived_is_hardcopy false derived_init_file_name pcie_onchip_memory2_0.hex generateLegacySim false

  

Software Assignments ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 CONTENTS_INFO "" DUAL_PORT 0 GUI_RAM_BLOCK_TYPE AUTO INIT_CONTENTS_FILE pcie_onchip_memory2_0 INIT_MEM_CONTENT 1 INSTANCE_ID NONE NON_DEFAULT_INIT_FILE_ENABLED 0 RAM_BLOCK_TYPE AUTO READ_DURING_WRITE_MODE DONT_CARE SINGLE_CLOCK_OP 0 SIZE_MULTIPLE 1 SIZE_VALUE 4096 WRITABLE 1

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pcie_hard_ip_0

altera_pcie_hard_ip v15.1

Parameters under_test 0 INTENDED_DEVICE_FAMILY STINGRAY pcie_qsys 1 p_pcie_hip_type 2 lane_mask 254 my_gen2_lane_rate_mode false max_link_width 1 p_pcie_txrx_clock 100 MHz p_pcie_app_clk 0 millisecond_cycle_count 125000 core_clk_freq 1250 p_pcie_test_out_width 64bits enable_gen2_core false gen2_lane_rate_mode false no_soft_reset false p_pcie_version 2.0 core_clk_divider 2 enable_ch0_pclk_out true core_clk_source pclk NUM_PREFETCH_MASTERS 1 CB_P2A_AVALON_ADDR_B0 0x00000000 bar0_size_mask 5 bar0_io_space false bar0_64bit_mem_space false bar0_prefetchable false CB_P2A_AVALON_ADDR_B1 0x00000000 bar1_size_mask 5 bar1_io_space false bar1_64bit_mem_space false bar1_prefetchable false CB_P2A_AVALON_ADDR_B2 0x00000000 bar2_size_mask 15 bar2_io_space false bar2_64bit_mem_space false bar2_prefetchable false CB_P2A_AVALON_ADDR_B3 0x00000000 bar3_size_mask 0 bar3_io_space false bar3_64bit_mem_space false bar3_prefetchable false CB_P2A_AVALON_ADDR_B4 0x00000000 bar4_size_mask 0 bar4_io_space false bar4_64bit_mem_space false bar4_prefetchable false CB_P2A_AVALON_ADDR_B5 0x00000000 bar5_size_mask 0 bar5_io_space false bar5_64bit_mem_space false bar5_prefetchable false fixed_address_mode 0 CB_P2A_FIXED_AVALON_ADDR_B0 0 CB_P2A_FIXED_AVALON_ADDR_B1 0 CB_P2A_FIXED_AVALON_ADDR_B2 0 CB_P2A_FIXED_AVALON_ADDR_B3 0 CB_P2A_FIXED_AVALON_ADDR_B4 0 CB_P2A_FIXED_AVALON_ADDR_B5 0 BAR 0,1,2,3,4,5 BAR Type 32 bit Non-Prefetchable,32 bit Non-Prefetchable,32 bit Non-Prefetchable,Not used,Not used,Not used BAR Size 5,5,15,0,0,0 Avalon Base Address 0,0,0,0,0,0 vendor_id 4466 device_id 4 revision_id 1 class_code 0 subsystem_vendor_id 4466 subsystem_device_id 4 port_link_number 1 msi_function_count 0 enable_msi_64bit_addressing true enable_function_msix_support false eie_before_nfts_count 4 enable_completion_timeout_disable false completion_timeout NONE enable_adapter_half_rate_mode false msix_pba_bir 0 msix_pba_offset 0 msix_table_bir 0 msix_table_offset 0 msix_table_size 0 use_crc_forwarding false surprise_down_error_support false dll_active_report_support false bar_io_window_size 32BIT bar_prefetchable 32 hot_plug_support 0 no_command_completed true slot_power_limit 0 slot_power_scale 0 slot_number 0 enable_slot_register false link_common_clock 1 advanced_errors false enable_ecrc_check false enable_ecrc_gen false my_advanced_errors false my_enable_ecrc_check false my_enable_ecrc_gen false max_payload_size 0 p_pcie_target_performance_preset High retry_buffer_last_active_address 255 credit_buffer_allocation_aux ABSOLUTE vc0_rx_flow_ctrl_posted_header 17 vc0_rx_flow_ctrl_posted_data 91 vc0_rx_flow_ctrl_nonposted_header 20 vc0_rx_flow_ctrl_nonposted_data 0 vc0_rx_flow_ctrl_compl_header 48 vc0_rx_flow_ctrl_compl_data 256 RX_BUF 9 RH_NUM 7 G_TAG_NUM0 32 endpoint_l0_latency 0 endpoint_l1_latency 0 enable_l1_aspm false l01_entry_latency 31 diffclock_nfts_count 255 sameclock_nfts_count 255 l1_exit_latency_sameclock 7 l1_exit_latency_diffclock 7 l0_exit_latency_sameclock 7 l0_exit_latency_diffclock 7 gen2_diffclock_nfts_count 255 gen2_sameclock_nfts_count 255 CG_COMMON_CLOCK_MODE 1 CB_PCIE_MODE 0 AST_LITE 0 CB_PCIE_RX_LITE 0 CG_RXM_IRQ_NUM 16 CG_AVALON_S_ADDR_WIDTH 20 bypass_tl false CG_IMPL_CRA_AV_SLAVE_PORT 1 CG_NO_CPL_REORDERING 0 CG_ENABLE_A2P_INTERRUPT 1 p_user_msi_enable 0 CG_IRQ_BIT_ENA 65535 CB_A2P_ADDR_MAP_IS_FIXED 0 CB_A2P_ADDR_MAP_NUM_ENTRIES 2 CB_A2P_ADDR_MAP_PASS_THRU_BITS 20 CB_A2P_ADDR_MAP_FIXED_TABLE_0_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_0_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_1_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_1_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_2_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_2_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_3_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_3_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_4_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_4_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_5_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_5_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_6_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_6_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_7_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_7_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_8_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_8_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_9_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_9_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_10_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_10_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_11_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_11_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_12_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_12_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_13_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_13_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_14_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_14_LOW 0 CB_A2P_ADDR_MAP_FIXED_TABLE_15_HIGH 0 CB_A2P_ADDR_MAP_FIXED_TABLE_15_LOW 0 Address Page 0,1,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A PCIe Address 63:32 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 PCIe Address 31:0 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 RXM_DATA_WIDTH 64 RXM_BEN_WIDTH 8 CB_TXS_ADDRESS_WIDTH 7 TL_SELECTION 1 pcie_mode SHARED_MODE single_rx_detect 1 enable_coreclk_out_half_rate false low_priority_vc 0 SLAVE_ADDRESS_MAP_0 5 SLAVE_ADDRESS_MAP_1 5 SLAVE_ADDRESS_MAP_2 15 SLAVE_ADDRESS_MAP_3 0 SLAVE_ADDRESS_MAP_4 0 SLAVE_ADDRESS_MAP_5 0 SLAVE_ADDRESS_MAP_1_0 0 SLAVE_ADDRESS_MAP_3_2 0 SLAVE_ADDRESS_MAP_5_4 0 deviceFamily STINGRAY wiz_subprotocol Gen 1-x1 link_width 1 cyclone4 1 AUTO_DEVICE EP4CGX15BF14C8 AUTO_DEVICE_SPEEDGRADE 8 AUTO_CAL_BLK_CLK_CLOCK_RATE 0 AUTO_CAL_BLK_CLK_CLOCK_DOMAIN 1 AUTO_CAL_BLK_CLK_RESET_DOMAIN 1 generateLegacySim false

  

Software Assignments (none)

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pio_0

altera_avalon_pio v15.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 32 clockRate 125000000 derived_has_tri false derived_has_out true derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 32 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 125000000 HAS_IN 0 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

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sysid_qsys_0

altera_avalon_sysid_qsys v15.1

Parameters id 538509842 timestamp 1553062488 AUTO_DEVICE_FAMILY STINGRAY deviceFamily Cyclone IV GX generateLegacySim false

  

Software Assignments ID 538509842 TIMESTAMP 1553062488